The present invention relates to ferromagnetic thin film memories and, more particularly, to ferromagnetic thin film memories in which states of the memory cells based on magnetization direction are determined through magnetoresistive properties of the thin film sensed by an electronic circuit.
Digital memories of various kinds are used extensively in computers and computer system components, in digital processing systems, and the like. Such memories can be formed, to considerable advantage, based on the storage of digital bits as alternative states of magnetization in magnetic materials in each memory cell, typically thin film materials. These films may be ferromagnetic thin films having information stored therein through the direction of the magnetization occurring in that film, with this information being obtained through either inductive sensing to determine the magnetization state, or by magnetoresistive sensing of such states. Such ferromagnetic thin film memories may be conveniently provided on the surface of a monolithic integrated circuit to provide easy electrical interconnection between the memory cells and the memory operating circuitry.
Ferromagnetic thin film memory cells can be made very small and packed very closely together to achieve a significant density of stored digital bits, properties which permit them to be provided on the surface of a monolithic integrated circuit as indicated above. One construction, as an example, is shown in FIG. 1, where a bit structure 10 for a memory cell that is presented is formed over a semiconductor material body 12, as used in a monolithic integrated circuit, and directly on an insulating layer 13, itself supported on a major surface of body 12 in the integrated circuit. Only a small portion of the integrated circuit is shown, and then only a small portion of the semiconductor body is shown in that integrated circuit portion.
These bit structures in an assemblage in a memory are usually provided in a series string of such bit structures often collectively called a sense line. There are typically a plurality of such sense lines in a memory. In order to make interconnections between members of such sense lines, or between the sense lines and the external circuitry in the integrated circuit for operating the memory, terminal regions or junctures 14 are typically provided at each end of the bit structure for interconnection purposes. These interconnections might be formed of copper alloyed in aluminum.
The remainder of the bit structure disposed on the exposed major surface of insulating layer 13 includes a lower ferromagnetic thin film 15 and an upper ferromagnetic thin film 16. Ferromagnetic thin film layers 15 and 16 typically exhibit uniaxial anisotropy, magnetoresistance, little magnetostriction, and are of an alloy composition typically comprising nickel, cobalt and iron. The magnetic device structure can be a spin valve that includes a pinned reference layer 15 spaced apart from a xe2x80x9cfree layerxe2x80x9d 16 that stores the digital information. The lower ferromagnetic thin film 15 is typically, but not always, thicker than the upper ferromagnetic thin film 16. Alternatively, a pseudo-spin-valve structure can be used where the lower ferromagnetic thin film 15 is often called the hard layer, and the upper ferromagnetic thin film 16 is often called the soft layer.
Between ferromagnetic thin film layers 15 and 16 is typically a further thin layer 17 which usually would not exhibit ferromagnetism but may be either an electrical conductor or an electrical insulator. Layer 17 must, however, in this construction, minimize the exchange interaction between layers 15 and 16 so that the magnetization vectors of each layer are decoupled. A typical choice for layer 17 would be copper. An insulating layer 18 covers bit structure 10 although only a part of it is shown in FIG. 1.
Finally, a word line 19 is shown in FIG. 1 disposed on the major surface of insulating layer 18. Word line 19 typically includes an aluminum layer alloyed with copper on a titanium-tungsten base layer. A protective and insulating layer over the entire structure of FIG. 1 is often used in practice, but is not shown here.
Bit structure 10 can be operated in a longitudinal mode having its easy axis extend between internal interconnections 14 perpendicular to the direction of word line 19. Information kept as a digital bit having one of two alternative logic values in bit structure 10 is stored therein in layer 15 by having the magnetization vector point in one direction or the other, generally along the easy axis of magnetization. If the direction of magnetization is caused to rotate from such a direction by external magnetic fields, the electrical resistance of layers 15 and 16 changes with this magnetization direction rotation because of the magnetoresistive properties of such layers. For the kinds of materials typically used in layers 15 and 16, the maximum change in resistance is on the order of a few percent of the minimum resistance value.
In the memory shown in FIG. 1, sense current refers to the current flow through bit structure 10 from one terminal 14 to the other terminal 14. Word current refers to current flow in word line 19 adjacent to, and transverse to the orientation of bit structure 10. Bit structure 10 can be placed in one of the two possible magnetization states of layer 15 (pinned layer) through the selective application of sense and word currents i.e., information can be xe2x80x9cwrittenxe2x80x9d in bit structure 10. A bit structure 10 of a typical memory configuration can be placed in a xe2x80x9c0xe2x80x9d magnetization state by the application of a sense current of typically 1.0 mA, and coincidentally with the provision of a word current in one direction from 20 mA to 40 mA. The opposite magnetization state representing a xe2x80x9c1xe2x80x9d logic value can be provided through providing the same sense current and a word current of the same magnitude in the opposite direction. Such states typically occur fairly quickly after the proper current levels are reached, such state changes typically occurring in less than about 5 ns.
Determining which magnetization state is stored in bit structure 10 i.e., reading the information stored in bit structure 10, is typically done by providing externally caused magnetic fields in that bit structure, through providing, for example, word line currents and coincident sense line currents. These currents rotate the magnetization of the upper ferromagnetic thin film 16 (free layer) of the bit structure 10. As indicated above, this causes a change in the electrical resistance encountered between terminal regions 14 in bit structure 10 for different magnetization directions in the structure, including changing from one easy axis direction magnetization state to the opposite direction state. As a result, there is detectable differences in the voltage developed across magnetic bit structure 10 by the sense current flowing therethrough, depending on the relative magnetization direction of the pinned and free layers of bit structure 10.
During a typical read procedure, a word line current is provided over a selected bit structure 10 in a first direction. The word line current produces an externally generated magnetic field in the bit structure 10. The magnitude of the word line current must be large enough to rotate the free layer 15 of the bit structure 10. A typical word line current is 10-20 mA.
A sense current is also provided to the sense line that includes the bit structure 10. Because each sense line typically includes a series string of bit structures, the sense current typically flows through all of the bit structures that are members of the selected sense line. The sense current is typically provided concurrent with the word line current, and the resulting voltage (resistance) across the sense line is sensed. If the magnetization of the free layer 16 is parallel to the magnetization of the pinned layer 15, the voltage (resistance) is in a lower state. If the magnetization of the free layer 16 is anti-parallel to the magnetization of the pinned layer 15, the voltage (resistance) is in a higher state. The sensed voltage (resistance) is then typically stored using an auto-zero circuit. The time required to sense the voltage (resistance) of the members in the sense line, including bit structure 10, is typically about 50 ns. This time is relatively long, at least in part, because of the noise generated by the relatively large word line current that is present during the sensing operation.
After the voltage (resistance) of the sense line is sensed with the word line current in the first direction, the word line current is typically reversed. The magnitude of the word line current is again large enough to rotate the free layer 15 of the bit structure 10. A sense current is then provided to the sense line that includes bit structure 10, concurrent with the word line current, and the resulting voltage (resistance) across the members of the sense line is again sensed. The time typically required to sense the voltage (resistance) of the sense line is about 50 ns. The sensed voltage (resistance) is then compared to the previously sensed voltage (resistance) stored by the auto-zero circuit. If the resistance change is positive, one logic state is read. If the resistance change is negative, the opposite logic state is read.
The above-described reading procedure suffers from a number of disadvantages. One disadvantage is that two separate read cycles are required to read the state of a memory element; one with the word line current in one direction and another with the word line current in the opposite direction. Because two read cycles are required, the read access time of the memory can be limited.
Another disadvantage of the above-described reading procedure is that the voltage (resistance) sensed during the first cycle is relatively close in value to the voltage (resistance) sensed during the second cycle. This is because the reading procedure senses the resistance of all of the bit structures in the sense line, and not just the desired bit structure 10. As indicated above, the maximum change in resistance for a typical magneto-resistive bit structure 10 is on the order of a few percent of the minimum resistance value. While this resistance change is already relatively small, the percentage resistance change is effectively reduced by the resistance of the other bit structures that are in the selected sense line. As a result, it can be difficult and time consuming to compare the two resistance values to determine the state of the selected bit structure 10. This can increase the read access time and reduce the reliability of the memory.
Another disadvantage of the above-described reading procedure is that a relatively large word line current (10-30 mA) must typically be provided throughout each sensing cycle. This is particularly problematic because each sensing cycle may take on the order of 50 ns to sense the voltage (resistance) of the bit structure 10. As such, the reading operation may consume a significant amount of power. A related limitation is that the relatively large word line current can also cause a significant amount of noise at the bit structure 10. This can reduce the signal-to-noise ratio on the sense lines and slow the sensing operation.
The present invention overcomes many of the disadvantages of the prior art by providing a magneto-resistive memory that can directly sense the resistive state of one or more magneto-resistive memory elements, and therefore does not require two separate read cycles to read the state of a memory cell. This increases the speed and reduces the power of the memory. In addition, a word line current is not required to read a desired magneto-resistive memory element. This also helps increase the speed and reduce the power of the memory.
In one illustrative embodiment of the present invention, the magneto-resistive memory includes an array of memory cells arranged into rows and columns, with each column having a bit line. Each memory cell preferably includes a magneto-resistive bit, with the first end of the magneto-resistive bit connected to the bit line. Each memory cell preferably also includes a switch that is coupled to the second end of the magneto-resistive bit for selectively providing a path for a sense current to flow from the bit line, through the selected magneto-resistive bit, and to a first predetermined voltage terminal such as ground.
To read a selected memory cell of the magneto-resistive memory, a sense current is provided to the bit line that is connected to the selected memory cell, and the switch in the selected memory cell is enabled. By activating the switch, the sense current provided on the corresponding bit line flows through the magneto-resistive bit of the selected memory cell and to a predetermined voltage (e.g. ground). The switch provides selectivity between the rows of memory cells in the magneto-resistive memory. In this configuration, the sense current produces a voltage on the corresponding bit line that reflects the resistive state of the magneto-resistive bit. A sense amplifier may then be used to sense the voltage on the bit line.
In another illustrative embodiment of the present invention, each column has two bit lines, and each memory cell has two magneto-resistive bits that are written into opposite resistive states. The first end of a first magneto-resistive bit is connected to a first bit line, and first end of a second magneto-resistive bit is connected to a second bit line. Each memory cell preferably also includes a switch that is coupled to the second end of the first magneto-resistive bit and the second end of the second magneto-resistive bit. The switch selectively provides a path for a first sense current to flow from the first bit line, through the first magneto-resistive bit, and to a predetermined voltage. The switch also may selectively provide a path for a second sense current to flow from the second bit line, through the second magneto-resistive bit, and to the predetermined voltage.
In this illustrative embodiment, a selected memory cell is read by providing a first sense current to the first bit line and a second sense current to the second bit line. The first sense current is preferably substantially identical to the second sense current. Then, the switch of the selected memory cell is enabled. This allows the first sense current to flow through the first magneto-resistive bit to produce a first voltage on the first bit line, and further allows the second sense current to flow through the second magneto-resistive bit to produce a second voltage on the second bit line. A sense amplifier may then be used to sense the differential voltage between the first bit line and the second bit line.
Once the magneto-resistive state of the selected memory cell is sensed, the sensed state may be stored in a storage element, such as a latch or register. In an illustrative embodiment, a latch is provided that includes a first inverter and a second inverter coupled together in a cross-coupled configuration. Each of the first and second inverters preferably has a positive supply terminal, a negative supply terminal, an input terminal and an output terminal. The positive supply terminal of the first and second inverters are preferably coupled to a power supply voltage, such as VDD. The latch may also include a load transistor for loading a state into the latch. The load transistor preferably has a source terminal coupled to the input terminal of the first inverter, a drain terminal coupled to the input terminal of the second inverter, and a gate terminal coupled to a load enable terminal.
In one illustrative embodiment, the first bit line is coupled to a first predetermined node of the first inverter, and the second bit line is connected to a second predetermined node of the second inverter. The first predetermined node and the second predetermined node are preferably either the input terminal or the negative supply terminal of the corresponding cross-coupled inverter.
Rather than coupling the first bit line and the second bit line directly to the predetermined nodes of the latch, it is contemplated that the first bit line and the second bit line may first be provided to a differential amplifier. The differential amplifier may amplify the differential signal between the first bit line and the second bit line before providing an amplified differential signal to the predetermined nodes of the latch. It is also contemplated that the differential voltage signal between the first and second bit lines, either amplified or not, may be coupled to the predetermined nodes of the latch via one or more switches, if desired, as further described below.